1. Field of the Invention
The present invention generally relates to image sensors and, more particularly, the present invention relates to image sensors with a function of amending a ramping slope.
A claim of priority is made to Korean Patent Application 2005-37223 filed on May 3, 2005, the disclosure of which is hereby incorporated by reference.
2. Description of the Related Art
Photodiodes are used in image sensors to transform optical signals into electrical analog signals. In order to display the output of the photodiodes (i.e., images) on display devices such as, for example, LCD monitors, it is generally necessary to convert the analogue signals into digital signals. Analogue-to-digital converters (ADC) are utilized for this purpose.
The resolution of an ADC generally correlates to the number of binary bits contained in the digital output. More bits in the digital output means greater sampling of the analogue input.
Various types of ADCs are used to obtain digital signals from analogue signals, including, for example, parallel-comparing ADCs, integral ADCs, staircase ADCs, tracking ADCs, and so on.
Integrating ADCs (also known as ramp-compare ADCs) in particular are used to transform analogue signals into digital signals with high precision. Generally, an integrating ADC includes a ramp voltage generator, a comparator, and a counter. During each sampling period, a ramp voltage from the generator is continuously compared by the comparator with an analogue input signal, and the counter outputs a digital value indicative of the time period expended for the ramp voltage to equal or exceed that analogue input voltage.
FIG. 1 is a graph showing the input-output pattern of a conventional analogue-digital converter (ADC) which includes a single slope integrating ADC circuit. In FIG. 1, the vertical axis represents the digital binary output value (i.e., the counter value) of the ADC, while the horizontal axis represents the analog input voltage of the ADC, i.e., the analog voltage supplied from a photodiode. By way of example, FIG. 1 shows the input-output pattern of a 10-bit ADC.
In FIG. 1, plot 2 depicts the “normal” input-output pattern corresponding to a desired design target. Plot 1 depicts a defective input-output pattern having a slope which is greater than that of plot 2, and plot 3 depicts a defective input-output pattern having a slope which is smaller than that of plot 2. The defective input-output patterns depicted by plots 1 and 3 may result from differing resistance values of resistors forming a ramping voltage generator of the ADC. This variance in resistor values generally results from process variations (e.g., implantation variations) inevitably encountered during manufacture of semiconductor devices. While defective input-output pattern characteristics of the ADCs can be improved with improvements in fabrication techniques, it is generally not possible to completely eliminate all process variations which might impact ADC input-output patterns.